This invention relates to a data processor with plural instruction execution parts, and it further relates to such methods as a method of synchronizing instruction executions, a method of saving an instruction address when an exception occurs, and a method of invalidating instruction processing when an exception occurs, in the aforesaid data processor.
For high-speed data processing, data processors with a plurality of instruction execution parts are known in the art. For example, there is a data processor in which instruction execution parts of different types (for example, one type for integer/logical operations and the other for floating-point operations) are independently arranged. Such difference in types of instruction execution parts usually results in different instruction execution time. Although the actual order of instruction executions may somewhat change, the contents of registers of the data processor at each time must be updated in the same order as that in which instructions are fed to be executed. This requirement will become more critical if the execution of an instruction is forced to be interrupted when an exception occurs. The control of the order of execution completion of instructions between one instruction execution part and the other (that is, synchronizing instruction executions) is important.
If an exception occurs when executing a certain instruction, its instruction address requires to be saved so that the instruction processing interrupted can resume starting with that instruction after exceptional handling. Further, the invalidation of instruction processing is required when an exception occurs, before re-executing instructions after exceptional handling.
Prior art data processors, however, have such a configuration that the addresses of instructions to be processed in a subordinate instruction execution part are also fed to a main instruction execution part for synchronization of instruction executions. As a result, a portion of the main instruction execution part is occupied by the addresses of instructions which are not processed in the main instruction execution part. This presents a problem that the processing of instruction execution cannot be carried out effectively because the main instruction execution part should deal with unnecessary instruction processing. Further, since the main instruction execution part holds the addresses of all instructions to be processed in itself and other instruction execution parts for saving their instruction addresses when an exception occurs, this requires more hardware in order to hold addresses in such a case that a great number of instructions are executed in parallel by many instruction execution parts as in a data processor employing super-scalar techniques. This causes a further barrier to meet demands for integrating many functions on a single chip of LSI.